In recent years, use of a low-dielectric-constant interlayer dielectric (hereinafter may be referred to as “low-dielectric-constant insulating film”) has been studied in order to prevent a signal delay due to multilayer interconnection of semiconductor devices. A material disclosed in JP-A-2001-308089 or JP-A-2001-298023 has been proposed as a material for the low-dielectric-constant insulating film, for example. When using the low-dielectric-constant insulating film as an interlayer dielectric, copper or a copper alloy is used as an interconnect material since high conductivity is required. When producing such a semiconductor device using a damascene process, a step of removing the interconnect material on the barrier metal film by chemical mechanical polishing (first polishing step), and a step of removing the barrier metal film by chemical mechanical polishing, and optionally chemically and mechanically polishing the interconnect material and the interlayer dielectric to implement planarization (second polishing step), are normally required.
In the first polishing step, only the interconnect material must be selectively polished at high speed. However, it is very difficult to implement a state in which dishing and erosion do not occur in the interconnect area when the first polishing step has completed (i.e., when the barrier metal film and the like have been exposed) while maintaining a high polishing rate of the interconnect material. For example, the polishing rate may be increased by increasing the polishing pressure so that a higher frictional force is applied to the wafer. However, since dishing and erosion of the interconnect area occur to a larger extent by increasing the polishing rate, an effect achieved by the polishing method is limited. In order to obtain an excellent polished surface by the second polishing step, it is necessary to suppress a copper residue on the fine interconnect pattern in the first polishing step.
It is difficult to eliminate a copper residue due to the first polishing step or remove a copper residue due to the first polishing step by a simple washing step by the current polishing methods while implementing high-speed polishing and high flatness. Therefore, development of a novel chemical mechanical polishing aqueous dispersion that solves the above problems has been desired.
The second polishing step is required to flatly polish the polishing target surface. A change in design of the structure of semiconductor devices has been studied in order to further improve the flatness of the polishing target surface achieved by the second polishing step. Specifically, when using a low-dielectric-constant insulating film that has low mechanical strength, a structure in which a cap layer made of silicon dioxide or the like is formed on the low-dielectric-constant insulating film, etc., has been studied since (1) surface defects (e.g., separation and scratches) may occur on the polishing target surface due to chemical mechanical polishing, (2) the polishing rate of the low-dielectric-constant insulating film significantly increases when polishing a wafer that has a fine interconnect structure so that a flat polished surface with high accuracy may not be obtained, and (3) the adhesion between the barrier metal film and the low-dielectric-constant insulating film is low, for example. In this case, the second polishing step is required to quickly remove the cap layer by polishing while reducing the polishing rate of the low-dielectric-constant insulating film as much as possible. Specifically, the polishing rate (RR1) of the cap layer and the polishing rate (RR2) of the low-dielectric-constant insulating film must satisfy the relationship “RR1>RR2”.
In order to prevent breakage of the low-dielectric-constant insulating film and interfacial separation between the low-dielectric-constant insulating film and the stacked material, the polishing pressure may be reduced to reduce the frictional force applied to the wafer. In this case, since the polishing rate decreases by reducing the polishing pressure, the production efficiency of semiconductor devices significantly decreases. In order to solve the above problems, WO 2007/116770 discloses increasing the polishing rate by adding a water-soluble polymer to the chemical mechanical polishing aqueous dispersion. However, the polishing rate achieved by this method in the second polishing step is not necessarily sufficient.
Therefore, development of a novel chemical mechanical polishing aqueous dispersion that can polish the barrier metal film and the cap layer at a high polishing rate and achieves high flatness while preventing damage to the low-dielectric-constant insulating film has been desired.
A chemical mechanical polishing aqueous dispersion normally includes abrasive grains and additive components. In recent years, the chemical mechanical polishing aqueous dispersion has been mainly developed while focusing on the combination of the additive components. On the other hand, JP-A-2003-197573 or JP-A-2003-109921 discloses improving the polishing performance by controlling the properties of the abrasive grains.
However, when using the abrasive grains disclosed in JP-A-2003-197573 or JP-A-2003-109921, since the abrasive grains contain a metal component (e.g., sodium), it is difficult to remove the metal component (e.g., sodium) that remains on the polishing target after polishing. This makes it difficult to apply the abrasive grains disclosed in JP-A-2003-197573 or JP-A-2003-109921 to polishing of actual devices. Moreover, the abrasive grains disclosed in JP-A-2003-197573 or JP-A-2003-109921 exhibit poor storage stability due to poor dispersion stability.